SoftIP IP Group of Alphawave IP
SoftIP IP Group of Alphawave IP

50G Ethernet PCS/MAC/FEC


The fully integrated Physical Coding Sublayer (PCS) and Media Access Controller (MAC) core for 50Gbps Ethernet applications are compliant with IEEE 802.3cd -2018 standard and Ethernet Technology Consortium 50GE standard. The interface to the PMA supports either 2x 25Gbps or a single 50Gbps bi-directional, serial interface. The PCS sublayer includes encoding, transcoding, scrambling, FEC layer, and symbol distribution.

The north-bound interface from the MAC provides a configurable n x 64-bit system interface.

The southbound interface performs the mapping of transmitting and receiving data streams (at the PMA layer) to the on-chip SERDES. This core is responsible for channel alignment and KP4 FEC management. The PCS supports an interface for 50GBASE-CR or 50GBASE-KR.


  • Proven IP reduces development time and risk
  • Upgrade process as the standard evolves
  • Supports both 50GBASE-KR2/1 and 50GBASE-CR2/1 PMD interfaces
  • Support both KR4 FEC (RS528,514) and KP4 FEC (RS544,514) modes
  • Support 25G NRZ SerDes and 56G PAM4 SerDes
  • Support for 2-lane or single-lane SERDES interface
  • Off-the-shelf, proven technology implementation in Altera and Xilinx FPGAs and ASIC SOC
  • Tested and interoperability-proven against Spirent and Viavi test equipment


  • High-performance server network interface cards
  • Mid-sized routers


  • Logic and power efficient KR4 and KP4 FEC engine with full warnings and alarms
  • Integrated 64B/66B and 256B/257B encoder for area efficiency
  • Built-in loopbacks and PRBS generators/ checkers for test and diagnostics
  • Fully compatible with IEEE802.3cd-2018 standard and Ethernet Technology Consortium 50GE standard
  • Super low latency with minimized fixed and variable delay for network efficiency.
  • Supports 1588v2 time stamps and full error handling
  • Supports 802.3br express traffic and 802.1Qbb priority flow control (PFC)

High-Speed Communication Core

All Precise-ITC cores have been tested on both Intel/Altera and Xilinx FPGA hardware. Precise-ITC partners with leading test equipment vendors like Spirent and Viavi to prove interoperability. SOC cores have been implemented with ASIC/FPGA partners using the latest technology nodes.

Precise-ITC cores are designed for efficiency. Built-in data buffers are efficiently implemented to reduce overall delay through the data path. Variable delay (or jitter) is tightly managed to ensure 1588v2 time-stamp accuracy. Precise-ITC can provide simulation models and routable RTL along with detailed interface documentation. Contact Precise-ITC for more information.