Canada Technology Innovation – ASIC, FPGA & Embedded Software !
Canada Technology Innovation – ASIC, FPGA & Embedded Software !

50G PCS/KP4 FEC and MAC IP Cores

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The fully integrated Physical Coding Sublayer (PCS) and Media Access Controller (MAC) core for 50Gbps Ethernet applications are compliant with IEEE 802.3cd -2018 standard and Ethernet Technology Consortium 50GE standard. The interface to the PMA supports either 2x 25Gbps or a single 50Gbps bi-directional, serial interface. The PCS sublayer includes encoding, transcoding, scrambling, FEC layer, and symbol distribution.

The north-bound interface from the MAC provides a configurable n x 64-bit system interface.

The southbound interface performs the mapping of transmitting and receiving data streams (at the PMA layer) to the on-chip SERDES. This core is responsible for channel alignment and KP4 FEC management. The PCS supports an interface for 50GBASE-CR or 50GBASE-KR.

Benefits

  • Proven IP reduces development time and risk
  • Upgrade process as the standard evolves
  • Supports both 50GBASE-KR2/1 and 50GBASE-CR2/1 PMD interfaces
  • Support both KR4 FEC (RS528,514) and KP4 FEC (RS544,514) modes
  • Support 25G NRZ SerDes and 56G PAM4 SerDes
  • Support for 2-lane or single-lane SERDES interface
  • Off-the-shelf, proven technology implementation in Altera and Xilinx FPGAs and ASIC SOC
  • Tested and interoperability-proven against Spirent and Viavi test equipment

Applications

  • High-performance server network interface cards
  • Mid-sized routers

Features

  • Logic and power efficient KR4 and KP4 FEC engine with full warnings and alarms
  • Integrated 64B/66B and 256B/257B encoder for area efficiency
  • Built-in loopbacks and PRBS generators/ checkers for test and diagnostics
  • Fully compatible with IEEE802.3cd-2018 standard and Ethernet Technology Consortium 50GE standard
  • Super low latency with minimized fixed and variable delay for network efficiency.
  • Supports 1588v2 time stamps and full error handling
  • Supports 802.3br express traffic and 802.1Qbb priority flow control (PFC)

50GBASE-R PCS Core Features

  • 64B/66B encoding of incoming MII signal
  • 256/257B transcoding (to reduce overhead for FEC insertion)
  • X58 Scrambling (optional bypass)
  • Idle block removal (to reduce overhead for AM insertion)
  • Alignment Marker (AM) insertion. Unique marker portion of AM for each lane is s/w configurable.
  • KP4 (RS544,514) Forward Error Correction (FEC) parity calculation and insertion with symbol distribution
  • Test pattern generation (scrambled idles)
  • Clause 45 MDIO register set
  • Error detection and interrupt reporting
  • Alignment marker removal (where applicable)
  • Unique marker portion of AM for each lane is s/w configurable (where applicable)
  • Alignment lock and lane deskew of up to 2 lanes
  • KP4 (RS544,514) FEC Decode and correction
  • X58 De-scrambling (optional bypass)
  • Reverse 256/257B transcoding
  • 64B/66B decoding to MII signal
  • Test pattern monitoring
  • Clause 45 MDIO register set
  • Error detection and interrupt reporting
  • Loopback from TX MII to RX MII
  • Performance Monitoring and Statistics
    • Dynamic skew measurement for each lane
    • PCS Status – link up/down
    • High bit error rate (hi-BER)
    • BER counter
    • Test pattern error counter
    • Multi-lane AM status (locked and aligned/not locked and aligned)
    • FEC Corrected code word count (with FEC enabled)
    • FEC Uncorrected code word count (with FEC enabled)
    • FEC symbol error counter (with FEC enabled)
    • FEC degrade SER (with FEC enabled)

50GBASE-R MAC Core Features

  • TX FCS calculation and insertion
  • TX MAC control frame generation
    • Unicast/Multicast PAUSE frame generation by MAC client or by software
    • Software configurable PAUSE quanta
  • TX Performance Monitoring and Statistics (counters are 36-bit to accommodate 1-second of statistic counts)
    • Byte count
    • Frame count
    • PAUSE frame count
    • Multicast frame count
    • Unicast frame count
    • Undersize frame count
    • Oversize frame count
    • Frame count statistic for the following sized frames:
      • 64
      • 65-127
      • 128-255
      • 256-511
      • 512-1023
      • 1024-1518
      • 1519-1522
      • 1523-1548
      • 1549-2047
      • 2048-4095
      • 4096-8191
      • 8192-9215 bytes
    • RX FCS check and removal
    • RX PAUSE frame processing and handling
    • RX Performance Monitoring and Statistics (counters are 36-bit to accommodate 1-second of statistic counts)
      • Bad FCS
      • Bad Preamble
      • Byte count
      • Frame count
      • PAUSE frame count
      • Multicast frame count
      • Unicast frame count
      • Bad FCS frame count
      • Bad frame count
      • Bad aligned frame count
      • Undersize frame count
      • Oversize frame count
      • Frame count statistic for the following sized frames:
        • 64 byte
        • 65-127
        • 128-255
        • 256-511
        • 512-1023
        • 1024-1518
        • 1519-1522
        • 1523-1548
        • 1549-2047
        • 2048-4095
        • 4096-8191
        • 8192-9215 bytes
  • 1588v2 time stamping
  • 802.3br Interspersing Express Traffic
  • 802.1Qbb Priority Flow Control (PFC) up to 8 priorities

High-Speed Communication Core

All Precise-ITC cores have been tested on both Intel/Altera and Xilinx FPGA hardware. Precise-ITC partners with leading test equipment vendors like Spirent and Viavi to prove interoperability. SOC cores have been implemented with ASIC/FPGA partners using the latest technology nodes.

Precise-ITC cores are designed for efficiency. Built-in data buffers are efficiently implemented to reduce overall delay through the data path. Variable delay (or jitter) is tightly managed to ensure 1588v2 time-stamp accuracy. Precise-ITC can provide simulation models and routable RTL along with detailed interface documentation. Contact Precise-ITC for more information.