2.5G/1000M/100M/10M Quad-Mode MAC IP Core
The fully integrated 2.5G/1000M/100M/10M Quad-mode Media Access Controller (MAC) core for Ethernet applications is compliant with IEEE 802.3 standard and RGMII specifications. The PHY interface supports both RGMII and GMII interfaces. This Quad-Mode Core is configurable through software register.
The west-bound interface from the MAC provides a configurable 32-bit system interface.
The east-bound interface performs the mapping of transmit and receive data streams (at the PHY layer) to the on-chip SERDES or external PHY chip.
Figure 1 Quad-Mode MAC Block Diagram
- Proven IP reduces development time and risk
- Support 2.5Gbps, 1000Mbps, 100Mbps and 10Mbps PHY interfaces
- Support GMII and RGMII interface natively
- Support Full duplex or half-duplex modes
- Support Carrier Extended and Link fault
- Off-the-shelf, proven technology implementation in FPGAs and ASIC SOC
- Tested and interoperability-proven
- Integrated Quad-mode operation MAC with RGMII and GMII interface for area efficiency
- Fully compatible with IEEE802.3 2015 standard, and RGMII specification 1.3 and 2.0
- Super low latency with minimized fixed and variable delay for network efficiency.
- Supports 1588v2 1-step and 2-step time stamps and full error handling
- Supports 802.1Qbb priority flow control (PFC)