Precise-ITC offers a dynamically reconfigurable Nx100G multi-lane OTN (Callisto) Muxponder SOC solution for 10/25/40/100GE or generic 10/25/40/100G CBR clients. The Callisto is a single SOC multi-lane muxponding solution for CBR clients via GMP mapping or packet client via GFP-F mapping. For packet/GFP-F mapping, oversubscription is supported with elastic buffer.
AES-GCM encryption and MAC/RS statistics and performance monitoring are optional add-on features to further enhance the power of Callisto SOC.
Each lane is individually configurable through an easy to use Software Application Programming Interface (API) or customizable software driver.
Figure 1 : Callisto Muxponder Lane Core Block Diagram
- Line Interface
- OTU4+G.709 GFEC
- OTL4.4 or OTL4.10 (with flexible deskew buffers)
- Client Interface
- 10/25/40/100G Etherent
- 10/25/40/100G CBR clients
- SFI-S (CBR client)
- Ethernet Media Access Control (MAC) + RS Link ( Optional )
- Ethernet frame delineation adhering to 802.3
- Statistics gathering
- AES-GCM Encryption at OPU layer ( Optional )
- 4x100G OPU4, 2xOPUC2 or 1xOPUC4 layer bulk encryption using AES-GCM
- Programmable encryption message size, dedicated SW key-exchange/messaging via ODU OH, NIST/FIPS compliance AES algorithm
- GFP-F Encapsulation and Delineation
- Compliant to G.7041
- Provides optional IDLE insertion and removal
- Support oversubscription with elastic packet buffer
- Generic Mapping Procedure (GMP)
- Client Signal mapping/de-mapping and rate adaption to/from OPU4
- Compliant with G.709
- OTN Mapper +GFEC
- Maps GMP mapped or GFP encapsulated payload to OPU4
- OPU/ODU/OTU Overhead generation including alarms. OH fields programmed through software registers or via an OH insertion interface.
- 709 GFEC generation
- Optional using external proprietary FEC encoding
- OTN De-mapper +GFEC
- ODU/OTU frame alignment with programmable FAS
- ODU/OTU overhead processing including detection of faults
- OTU/ODU/OPU overhead monitoring. Capture of registers for software processing of slow changing fields or option to send to an OH extraction interface for processing by an external device.
- 709 GFEC decode processing
- Optional using external proprietary FEC decoding
- Processor Interface
- Simple request-acknowledge register access to 32-bit registers for device configuration and statistic collection.
- Optional AXI4-lite interface
- Application Programming Interface
- Complete API for ease of use for configuration, error processing and monitoring.
Callisto is a multi-lane muxponder FPGA solution for 10/25/40/100G Ethernet or 10/25/40/100G CBR clients onto Optical Transport Network (OTN). Each lane can be configured independently.
For client mapping, the core can perform constant bit-rate (CBR) async mapping using GMP or packet mapping using GFP. With packet mapping, a bandwidth buffer is used for bandwidth management between the GFP mapper and the packet clients.The 10/25/40G CBR or packet clients are first mapped into LO ODU2, LO ODUFLEX or LO ODU3 via GMP or GFP-F and then multiplexed into ODTUmux and then to HO OPU4. The 100G client will map directly onto HO OPU4 via GMP.
The OTU4 core of Callisto supports 3 levels of OH insertions and extractions : register programming, memory programming and external programming via a dedicated OH port. The gFEC function can be disabled (or removed to save area) and a custom high-gain FEC can be used. The OTU4 core supports full alarm and OH inserts and extracts as specified in ITU G.709 and ITU G.798.
The following shows a few examples of how Callisto can be configured for different applications:
- 4x25GBASE-R <> LO ODUFLEX <> HO OPU4 <> OTU4+GFEC <> OTL4.4
- 10x10GBASE-R <> TTT 10xLO ODU2 <> HO OPU/ODU4 <> OTU4+GFEC <> OTL4.4/OTL4.10
- 2x10GBASE-R + 2x40GBASE-R <> TTT 2xLO ODU2 + 2xLO ODU3 <> HO OPU/ODU4 <> OTU4+GFEC <> OTL4.4/OTL4.10
- Customer specific muxponding lane configuration
- 100GBASE-R <> CAUI/CAUI4 <> Ethernet Mac <> GFP-F <> OPU/ODU4 <> OTU4+GFEC <> OTL4.4/OTL4.10
- 100GBASE-R <> CAUI/CAUI4 PCS-R/MLD <> GMP <> OPU/ODU4 <> OTU4+GFEC <> OTL4.4/OTL4.10
- 100G CBR <> SFI-S <> GMP <> OPU/ODU4 <> OTU4+GFEC <> OTL4.4/OTL4.10
Each lane is independent and can be dynamically re-configured to perform a different function without affecting the other lanes in mission.
Our SOC solution can offer much higher lane (port) density per chip, typically 1-4 depending on ASIC/FPGA sizes. As a result of higher port density, better power efficiency and cost effectiveness can be obtained.