Canada Technology Innovation – ASIC, FPGA & Embedded Software !
Canada Technology Innovation – ASIC, FPGA & Embedded Software !

Epak 100G_ZX

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1G-100G Ethernet/FiberChannel/FlexO Core

The 1G-100G Multi-channel Multi-rate Ethernet/FiberChannel/FlexO Core (Epak100G_ZX) core from Precise-ITC is a multi-rate Ethernet aggregator that supports tributaries at 1GE, 10GE, 25GE, 40GE, 50GE, 100GE in combinations up to 100G for Epak100G_ZX.

This core implements multi-rate Ethernet PCS and MAC. This versatile device allows users to add or drop sub-channels (for example 10GE) or merge channels (for example 4x25G = 100GE). These dynamic changes do not affect traffic on existing channels.

The north-bound interface from the multi-channel MAC provides a configurable system interface. The Multi-channel MAC manages the mapping between individual MACs and the assigned I/O or I/O group.

The southbound interface is mapped (at the PMA layer) to the on-chip SERDES. The core is responsible for channel alignment and FEC (where applicable).

Benefits

  • Combines Ethernet streams at a variety of rates to a single multi-channel interface at the MAC
  • The Epak100G_ZX allows access connections supporting 1GE, 10GE, 25GE, 40GE, 50GE and 100GE in any combination on any port or groups of ports to a maximum total bandwidth of 100Gbps
  • Dynamically change rate on any port without affecting existing traffic
  • Off-the-shelf, proven technology implementation in ASIC SOC
  • Tested and interoperability-proven against Spirent and Viavi test equipment

Features

  • Support any ethernet combinations (table 1) to maximum data-rate of the device
  • Fully compatible with IEEE802.3 2018 and IEEE 802.3 Standards
  • Support all IEEE802.3 PCS, FEC, and MAC statistics and alarms, and more
  • Optional add-on of ultra Low latency and area efficient FEC Core supports FC FEC RS (2112, 20280)
  • Support HiGig, HiGig+ and HiGig-lite
  • Optional Add-on with 66B ports to support FC800, FC1200 and FC1600 and their FC2 Monitoring
  • Support 1588v2 time stamps and full error handling
  • Support 802.1Qbb priority flow control (PFC)
Table 1 Support the following ethernet combinations
Serdes Rate Epak40G Epak100
1GE 4 10
10GE 4 10
25GE 1 or 4* 4
40GE 1 2
50GE * 1** 2**
100GE 0 1
Serdes assumes to be 10G. * for 25G serdes.** for 12.5G.

High-Speed Communication Cores

All Precise-ITC cores have been tested on both Intel/Altera and Xilinx FPGA hardware. Precise-ITC partners with leading test equipment vendors like Spirent and Viavi to prove interoperability. SOC cores have been implemented with ASIC/FPGA partners using the latest technology nodes.v

Precise-ITC cores are designed for efficiency. Built-in data buffers are efficiently implemented to reduce overall delay through the data path. Variable delay (or jitter) is tightly managed to ensure 1588v2 time-stamp accuracy. Precise-ITC can provide simulation models and routable RTL along with detailed interface documentation. Contact Precise-ITC for more information.