The Precise-ITC Scalable Serdes Framer Interface Digital Core IP implements the digital portion of the SFI-5 interface (OIF-SFI5-01.02). The SFI-S interface has up to a 50 Gbps bi-directional bit-rate and is used to connect communication microchips. It supports 16 lanes of data plus a deskew channel. Each lane has a bit-rate of 2.488 to 3.125 Gbps to support SONET OC-768, SDH STM-256, OTN OTU-3, and other systems operating in the range of 40 Gbps to 50 Gbps.
It features a flexible, parameterized design with a small footprint, easily tailored for your specific application.
Key Features
- Fully compliant with OIF-SFI5-01.02
- Independent transmit and receive blocks, each with 16 data lanes and a deskew channel
- Provides easy I/O connections to Serdes components
- Optional processor interface with 32-bit registers
Transmit
- Optional Receive Data Clock (RXDCK) generation
- Receive Status (RXS) generation to indicate alarm status
- Programmable PHY output lane swap
- Programmable deskew (DSC) channel framing bytes and expansion header
- Supports fixed and PRBS test pattern generation. Test pattern can be assigned to an individual lane or striped across data lanes
Receive
- Supports parameterized maximum lane-to-lane deskew e.g. +/- 32 UI
- Detects deskew channel loss of frame synchronization (LOF)
- Monitors Receive Status (RXS)
- Counts number of deskew channel mismatch errors
- Programmable PHY input lane swap
- Programmable deskew (DSC) channel framing bytes and expansion header
- Supports fixed and PRBS test pattern monitoring. Test pattern can be assigned to an individual lane or striped across data lanes