25G/10G/2.5G/1G Quad-Mode Ethernet MAC
The fully integrated Physical Coding Sublayer (PCS), KR FEC (IEEE Clause 74 – fire code FEC), SGMII / 1000BASE-X and Media Access Controller (MAC) core for 25Gbps, 10Gbps, 2.5Gbps/1.25Gbps Ethernet applications is compliant with IEEE 802.3 standard and SGMII specification 1.6. The interface to the PMA supports a single channel Quad-mode bi-directional, serial interface. The PCS sublayer supports both 64/66B encoding (10GE) and 8B10B encoding (SGMII/1000BASE-X) with an optional FEC layer function for backplane (10G-KR) application. This Quad-Mode Core is configurable through software register.
The east-bound interface from the MAC provides a configurable 64-bit system interface.
The bound interface performs the mapping of transmit and receive data streams (at the PMA layer) to the on-chip SERDES.
Figure 1 25G/10G/2.5G/1.25G Quad-Mode Code Block Diagram
- Proven IP reduces development time and risk
- Support 10GGBASE-R/KR/XFI and 1000BASE-KX PMD interfaces
- Support 25G/10G/SGMII/1000BASE-X PCS encoding
- Support for a single-lane SERDES interface
- MAC rate at 25G/10G/2.5G/1G
- Optional FC FEC (RS 2112,2080) – IEEE 802.3 Clause 74 support in 10GBASE-KR mode
- Off-the-shelf, proven technology implementation in FPGAs and ASIC SOC
- Tested and interoperability-proven against Spirent and Viavi test equipment
- Integrated MAC and PCS for area efficiency
- Fully compatible with IEEE802.3 2015 standard and SGMII specification 1.6 Standard
- Super low latency with minimized fixed and variable delay for network efficiency.
- Supports 1588v2 1-step and 2-step time stamps and full error handling
- Supports 802.1Qbb priority flow control (PFC)
- High performance server network interface cards
- Mid-sized routers