Canada Technology Innovation – ASIC, FPGA & Embedded Software !
Canada Technology Innovation – ASIC, FPGA & Embedded Software !

MCMR 400GE (Epak 400G/200G/100G IP)

EN/

Multi-channel Multi-rate 400G/200G/100G Ethernet Package – Epak 400G/200G/100G IP Core

The Epak SOC core from Precise-ITC is a multi-rate Ethernet aggregator that supports tributaries at 10GE, 25GE, 40GE, 50GE, 100GE and 200GE in combinations up to 100GE for the Epak100, 200GE for the Epak200 or 400GE for the Epak400.

The Epak cores provide FlexE 2.1/2.0/1.1/1.0 functionality and implement multi-rate Ethernet PCS and MAC. This versatile device allows users to add or drop sub-channels (for example 10GE) or merge channels (for example 4x25G = 100GE). These dynamic changes do not affect traffic on existing channels.

The north-bound interface from the multi-channel MAC provides a configurable system interface. The Multi-channel MAC manages the mapping between individual MACs and the assigned I/O or I/O group.

The southbound interface is mapped (at the PMA layer) to the on-chip SERDES. The core is responsible for channel alignment and FEC (where applicable).

Benefits

  • Combines Ethernet streams at a variety of rates to a single multi-channel interface at the MAC
  • The Epak100 allows access connections supporting 10GE, 25GE, 40GE, 50GE, and 100GE in any combination on any port or groups of ports to a maximum total bandwidth of 200Gbps
  • The Epak200 allows access connections supporting 10GE, 25GE, 40GE, 50GE, 100GE and 200GE in any combination on any port or groups of ports to a maximum total bandwidth of 200Gbps
  • The Epak400 allows access connections supporting 10GE, 25GE, 40GE, 50GE, 100GE, 200GE and 400GE in any combination on any port or groups of ports to a maximum total bandwidth of 400Gbps
  • Dynamically change rate on any port without affecting existing traffic
  • Off-the-shelf, proven technology implementation in FPGAs and ASIC SOC
  • Tested and interoperability-proven against Spirent and Viavi test equipment

Supported Ethernet Protocols and rates

Features

  • Supports any ethernet combinations (table 1) to maximum data-rate of the device (100G, 200G or 400G)
  • Fully compatible with IEEE 802.3 2015 and IEEE 802.3 Standards
  • UltraLow latency and area efficient FEC Core supports LL FEC RS(272,258), KP4 FEC RS(544,514), KR4 FEC RS(528,514) and FC FEC RS(2112,2080)
  • Support HiGig, HiGig+ and HiGig-lite
  • Support FlexE, OTN, FlexO, OTU25/50-RS, xGFC access ports
  • Support 10GFC to 256GFC Monitoring
  • Supports 1588v2 time stamps and full error handling
  • Supports 802.3br interspersing express traffic and 802.1Qbb priority flow control (PFC)
  • Flexible FlexE 2.1/2.0/1.1/1.0 core Add-on

Applications

  • High-density routers for data centers
  • Access switches

400G/200G/100G/50G/40G/25G/10G BASE-R PCS Core Features

PCS TX Core

  • 256/257B transcoding (to reduce overhead for FEC insertion) (not applicable for 10GE)
  • X58 Scrambling (optional bypass) (not applicable for 10GE)
  • 64B/66B encoding of incoming MII signal
  • Idle block removal (to reduce overhead for AM insertion)
  • Alignment Marker (AM) insertion. Unique marker portion of AM for each lane is s/w configurable.
  • Test pattern generation (scrambled idles)
  • Clause 45 MDIO register set
  • Error detection and interrupt reporting

Specific Feature for 400GBASE-KP4/200GBASE-KP4

  • KP4 (RS544,514) Forward Error Correction (FEC) parity calculation and insertion (2x interleaved) with symbol distribution

Specific Feature for 100GBASE-KP4/KR2/CR2 and 50GBASE-KR

  • KP4 (RS544,514) Forward Error Correction (FEC) parity calculation and insertion with symbol distribution

Specific Feature for 100GBASE-KR4/CR4 and 25GBASE-KR

  • KR4 (RS528,514) Forward Error Correction (FEC) parity calculation and insertion with symbol distribution

PCS RX Core

  • 64B/66B decoding to MII signal
  • Reverse 256/257B transcoding (not applicable to 10GE)
  • X58 De-scrambling (optional bypass) (not applicable for 10GE)
  • Alignment marker removal (where applicable)
  • Unique marker portion of AM for each lane is s/w configurable (where applicable)
  • Test pattern monitoring
  • Clause 45 MDIO register set
  • Error detection and interrupt reporting
  • Loopback from TX MII to RX MII
  • Performance Monitoring and Statistics
    • Dynamic skew measurement for each lane
    • PCS Status – link up/down
    • High bit error rate (hi-BER)
    • BER counter
    • Test pattern error counter
    • Multi-lane AM status (locked and aligned/not locked and aligned)
    • FEC Corrected code word count (with FEC enabled)
    • FEC corrected 1s and 0s counts
    • FEC Uncorrected code word count (with FEC enabled)
    • FEC symbol error counter (with FEC enabled)
    • FEC Hi-SER, Remote SER, degrade detection SER (with FEC enabled)

Specific Feature for 400GBASE-KP4/200GBASE-KP4

  • Alignment lock and lane deskew of up to 16 lanes (400GE) or up to 8 lanes (per 200GE).
  • Lane reordering
  • KP4 (RS544,514) FEC decoding and error correction (2x interleaved)

Specific Feature for 100GBASE-KP4/KR2/CR2 and 50GBASE-KR

  • Alignment lock and lane deskew of up to 4 lanes per 100GE
  • KP4 (RS544,514) FEC Decode and correction

Specific Feature for 100GBASE-KR4/CR4 and 25GBASE-KR

  • Alignment lock and lane deskew of up to 4 lanes per 100GE
  • KR4 (RS528,514) FEC decoding and correction

400G/200G/100G/50G/40G/25G/10G MAC Core Features (per channel)

  • TX FCS insertion
  • TX MAC control frame generation
    • Unicast/Multicast PAUSE frame generation by MAC client or by software
    • Software configurable PAUSE quanta
  • TX Performance Monitoring and Statistics
  • (counters are 36-bit to accommodate 1-second of statistic counts)
    • Byte count
    • Frame count
    • PAUSE frame count
    • Multicast frame count
    • Unicast frame count
    • Undersize frame count
    • Oversize frame count
    • Frame count statistic for the following sized frames:
      • 64
      • 65-127
      • 128-255
      • 256-511
      • 512-1023
      • 1024-1518
      • 1519-1522
      • 1523-1548
      • 1549-2047
      • 2048-4095
      • 4096-8191
      • 8192-9215
      • >9215
    • RX FCS check and removal
    • RX PAUSE frame processing and handling
  • RX Performance Monitoring and Statistics (counters are 36-bit to accommodate 1-second of statistic counts)
    • Bad FCS
    • Bad Preamble
    • Byte count
    • Frame count
    • PAUSE frame count
    • Multicast frame count
    • Unicast frame count
    • Bad FCS frame count
    • Bad frame count
    • Bad aligned frame count
    • Undersize frame count
    • Oversize frame count
    • Frame count statistic for the following sized frames:
      • 64 byte
      • 65-127
      • 128-255
      • 256-511
      • 512-1023
      • 1024-1518
      • 1519-1522
      • 1523-1548
      • 1549-2047
      • 2048-4095
      • 4096-8191
      • 8192-9215
      • >9215

Additional Add-on features

  • HiGig, HiGig+ and HiGig-lite
  • FlexE, FlexO, OTN, OTU25/50-RS access ports
  • 10GFC to 256GFC Monitoring
  • 1588v2 time stamping
  • 802.3br Express Traffic
  • 802.1Qbb Priority Flow Control (PFC) up to 8 priorities

High-Speed Communication Cores

All Precise-ITC cores have been tested on both Intel/Altera and Xilinx FPGA hardware. Precise-ITC partners with leading test equipment vendors like Spirent and Viavi to prove interoperability. SOC cores have been implemented with ASIC/FPGA partners using the latest technology nodes.

Precise-ITC cores are designed for efficiency. Built-in data buffers are efficiently implemented to reduce overall delay through the data path. Variable delay (or jitter) is tightly managed to ensure 1588v2 time-stamp accuracy. Precise-ITC can provide simulation models and routable RTL along with detailed interface documentation. Contact Precise-ITC for more information.