SoftIP IP Group of Alphawave IP
SoftIP IP Group of Alphawave IP



The fully integrated PCS/FEC Layer core for 25Gbps Ethernet, FibreChannel 32GFC and CPRI-10 applications is complaint with IEEE 802.3by-2016 standard, ANSI Fibre Channel- Framing and Signaling (FC-FS-4/5) and Common Public Radio Interface (CPRI) Interface Specification, V7.0 (2015-10-09). The interface to the PMA supports either 1x 25Gbps or a single 25Gbps bi-directional, serial interface.

The IP core supports both 25GE FEC layer, 32GFC and CPRI-10 FEC layer functions. The configuration is dynamically switchable via software register.

The north-bound interface from the MAC/PCS provides a 66-bit PCS interface or 66B OTN mapping layer.

The southbound interface performs the mapping of transmit and receive data streams (at the PMA layer) to the on-chip SERDES. This core is responsible for channel alignment and KR4 FEC management. The PCS supports an interface for 25GBASE-CR or 25GBASE-KR.




  • Proven IP reduces development time and risk
  • Upgrade process as the standard evolves
  • Supports both 25GBASE-KR and 25GBASE-CR PMD interfaces
  • Supports CPRI-10 PMD interface
  • Supports 32GFC PMD interface
  • Support next generation 25G NRZ SerDes
  • Support for a single-lane SERDES interface
  • Off-the-shelf, proven technology implementation in FPGAs and ASIC SOC
  • Tested and interoperability-proven against Spirent and Viavi test equipment


  • High-performance server network interface cards
  • Mid-sized routers




  • Logic and power efficient KR4 FEC engine with full warnings and alarms
  • Integrated 64B/66B and 256B/257B encoder for area efficiency
  • Automatic rate-adjustment between MAC/RS and PCS/FEC layers [25GE mode only]
  • Seamless
  • Built-in loopbacks and PRBS generators/ checkers for test and diagnostics
  • Fully compatible with IEEE802.3 2015 and IEEE 802.3by-2016, ANSI Fibre Channel- Framing and Signaling (FC-FS-4/5) and CPRI V7.0 Standards
  • Super low latency with minimized fixed and variable delay for network efficiency.
  • Software configurable between 25GE and CPRI-10 modes
  • Provide dynamic latency feedback to upper layer MAC/1588 timestamping logic to improve timestamp accuracy. [Optional]
  • Support 80-bit, 40-bit, 64-bit and 32-bit PMA interfaces

IP Core Features

  • 64B/66B Block synchronization and LF/RF/IDLE replacement signal generation
  • 256/257B transcoding (to reduce overhead for FEC insertion)
  • X58 Scrambling (optional bypass)
  • Idle block removal (to reduce overhead for AM insertion)
  • Alignment Marker (AM) insertion.  Unique marker portion of AM for each lane is s/w configurable [25GE mode only]
  • KR4 (RS528,514) Forward Error Correction (FEC) parity calculation and insertion with symbol distribution
  • Test pattern generation (scrambled idles)
  • PN-5280 scrambling [CPRI-10 mode only]
  • TX PCS and MAC RMON statistics [25GE mode only]
  • Clause 45 MDIO register set
  • Error detection and interrupt reporting
  • Alignment lock and removal [25GE mode only]
  • Sync and Test module [CPRI-10 mode only]
  • KR4 (RS528,514) FEC Decode and correction
  • X58 De-scrambling (optional bypass)
  • Reverse 256/257B transcoding
  • RX PCS and MAC RMON statistics [25GE mode only]
  • Test pattern monitoring
  • Clause 45 MDIO register set
  • Error detection and interrupt reporting
  • Performance Monitoring and Statistics
    • PCS Status – link up/down
    • High bit error rate (hi-BER)
    • BER counter
    • Test pattern error counter
    • AM status (locked and aligned/not locked and aligned)
    • FEC Corrected code word count (with FEC enabled)
    • FEC Uncorrected code word count (with FEC enabled)
    • FEC symbol error counter (with FEC enabled)
    • FEC degrade SER (with FEC enabled)

High-Speed Communication Core

All Precise-ITC cores have been tested on both Intel/Altera and Xilinx FPGA hardware. Precise-ITC partners with leading test equipment vendors like Spirent and Viavi to prove interoperability. SOC cores have been implemented with ASIC/FPGA partners using the latest technology nodes.

Precise-ITC cores are designed for efficiency. Built-in data buffers are efficiently implemented to reduce overall delay through the data path. Variable delay (or jitter) is tightly managed to ensure 1588v2 time-stamp accuracy. Precise-ITC can provide simulation models and routable RTL along with detailed interface documentation. Contact Precise-ITC for more information.