Canada Technology Innovation – ASIC, FPGA & Embedded Software !
Canada Technology Innovation – ASIC, FPGA & Embedded Software !

MCMR 800GE (Epak 800G IP)

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Multi-channel Multi-rate 800G Ethernet Package
– Epak 800G IP Core

The Epak SOC Core from Precise-ITC is a multi-rate Ethernet aggregator that supports tributaries from 800GE, to 1GE. E-pak 800G is our 3rd generation of Epak solution utilizing the 112G/s serdes and 56G/s serdes.

The supported ethernet protocols are 800GE, 400GE, 200GE, 100GE, 50GE, 40GE, 25GE, 10GE, 1GE, 10GFC, 16GFC, 32GFC, 64GFC, 128GFC, 256GFC as well as FEC framing of FlexO-1/2/4-SR. It supports any legal combination of Ethernet/Fiberchannel/FlexO rate up to 800G. This Core supports up to a maximum of 8 ethernet channel and works most effective and efficient with latest 112G/s serdes. With Core clock frequency of 1.6GHz at 7nm or 5nm, this Core delivers smallest footprint among similar solution in the Ethernet/Fiberchannel/ FlexO SOC market.

800GE Support

The Core supports 800GE which uses a full 800GE MAC and a pair of “bonded” 2 x 400GE PCS. The 800GE takes advantage of 112G/s serdes and uses virtual logical lanes in a “bonded” 2 x 400GE PCS. This improves power efficiency in 800G operation. The 800GE is compliant to the Ethernet Technology Consortium Standard.

Overview

The north-bound interface from the multi-channel MAC provides a configurable system interface. The Multi-channel MAC manages the mapping between individual MACs and the assigned I/O or I/O group.

The southbound interface is mapped (at the PMA layer) to the on-chip SERDES. The core is responsible for channel alignment and FEC (where applicable).

Benefits

  • Combines Ethernet streams at a variety of rates to a single multi-channel interface at the MAC
  • The Epak800 allows access connections supporting 1GE, 10GE, 25GE, 40GE, 50GE, 100GE, 200GE, 400GE, and 800GE in any combination on any port or groups of ports to a maximum total bandwidth of 800Gbps
  • Support IEEE 802.3 required FEC variances – LL FEC RS (272,258), KR4 FEC RS (528,514), KP4 FEC RS (544,514), FC FEC (2112,2080)
  • Support all IEEE802.3 PCS, FEC, and MAC statistics and alarms, and more
  • Supports HiGig, HiGig+ and HiGig-Lite
  • Dynamically change rate on any port without affecting existing traffic
  • Ethernet Technology Consortium 800GE supports with bonded 2 x 400GE PCS and a single 800G MAC
  • Fully utilize the advantages of 112G serdes to get highest possible port density per 800G.
  • Provide OTN, FlexE, FlexO, OTU25/50-RS, xGFC access ports
  • Optional FC1200 to 256GFC FC2 Monitoring
  • Ultra low latency and power efficient FEC engine
  • Support 1588, 802.1Qbb (PFC) and 802.3br express traffic (TSN).

Applications

  • High-density routers for data centers
  • Access switches

Table 1: Example Configurations of PCS Core

PCS Channel Type Num Channel(s)
with 16 x 56G Serdes Config
Num Channel(s)
with 8 x 112G Serdes Config
KP4 FEC KR4 FEC FC FEC No FEC
800GBASE-R8   1        
800GBASE-R16 1          
400GBASE-R16 1   X      
400GBASE-R8 2 1 X      
400GBASE-R4 2 X      
200GBASE-R8  2  1 X      
200GBASE-R4 4 2 X      
200GBASE-R2 4 X      
100GBASE-R4  4 X X   X
100GBASE-R2 8 4 X      
100GBASE-R1   8 X      
50GBASE-R4 4 2       X
50GBASE-R2 8 4 X X    
50GBASE-R1 16 8 X      
40GBASE-R4 4 2     X X
25GBASE-R1 16 8   X X X
10GBASE-R 16 8     X X
1GBASE-X / SGMII / 100M /10M 16 8       X

800GE BASE-R PCS Core Features

  • PCS layer formed by bonded 2x 400GE PCS in PCS Layer
  • Using 32 virtual logical lanes based on 2x400GE PCS to reduce power in 800G operation
  • Well designed into using 112G/s Serdes to provide highest port density for 800G Ethernet solution.

400G/200G/100G/50G/40G/25G/10G BASE-R PCS Core Features

PCS TX Core

  • 256/257B transcoding (to reduce overhead for FEC insertion) (not applicable for 10GE)
  • X58 Scrambling (optional bypass) (not applicable for 10GE)
  • 64B/66B encoding of incoming MII signal
  • Idle block removal (to reduce overhead for AM insertion)
  • Alignment Marker (AM) insertion. Unique marker portion of AM for each lane is s/w configurable.
  • Test pattern generation (scrambled idles)
  • Clause 45 MDIO register set
  • Error detection and interrupt reporting

Specific KP4 FEC Feature for 800GBASE-R/400GBASE-KP4/200GBASE-KP4/100GBASE-KP/50GBASE-KP

  • KP4 (RS544,514) Forward Error Correction (FEC) parity calculation and with symbol distribution

Specific KR4 FEC Feature for 100GBASE-KR4/CR4, 50GBASE-KR2 and 25GBASE-KR

  • KR4 (RS528,514) Forward Error Correction (FEC) parity calculation and insertion with symbol distribution

Specific FC FEC Feature for 50GBASE-R4, 40GBASE-R, 25GBASE-R and 10GBASE-R

  • RS (2112,2080) Forward Error Correction (FEC) parity calculation and insertion

PCS RX Core

  • 64B/66B decoding to MII signal
  • Reverse 256/257B transcoding (not applicable to 10GE)
  • X58 De-scrambling (optional bypass) (not applicable for 10GE)
  • Alignment marker removal (where applicable)
  • Unique marker portion of AM for each lane is s/w configurable (where applicable)
  • Test pattern monitoring
  • Clause 45 MDIO register set
  • Error detection and interrupt reporting
  • Loopback from TX MII to RX MII
  • Performance Monitoring and Statistics
    • Dynamic skew measurement for each lane
    • PCS Status – link up/down
    • High bit error rate (hi-BER)
    • BER counter
    • Test pattern error counter
    • Multi-lane AM status (locked and aligned/not locked and aligned)
    • FEC Corrected code word count (with FEC enabled)
    • FEC corrected 1s and 0s counts
    • FEC symbol error histogram for KP, KR FEC, and FC FEC
    • FEC Uncorrected code word counts
    • FEC symbol error counters
    • FEC degrade SER
    • FEC Hi-SER alarm

Specific KP4 FEC Feature for 800GBASE-R/400GBASE-KP4/200GBASE-KP4/100GBASE-KP/50GBASE-KP

  • Alignment lock and lane deskew
  • Lane reordering
  • KP4 (RS544,514) FEC decoding and error correction

Specific KR4 FEC Feature for 100GBASE-KR4/CR4, 50GBASE-KR2 and 25GBASE-KR

  • Alignment lock and lane deskew
  • KR4 (RS528,514) FEC decoding and correction

Specific FC FEC Feature for 50GBASE-R4, 40GBASE-R, 25GBASE-R and 10GBASE-R

  • Alignment sync
  • FC FEC (RS2112,2080) FEC
    decoding and correction

800G/400G/200G/100G/50G/40G/25G/10G MAC Core Features (per channel)

  • TX FCS insertion
  • TX MAC control frame generation
    • Unicast/Multicast PAUSE frame generation by MAC client or by software
    • Software configurable PAUSE quanta
  • TX Performance Monitoring and Statistics (counters are 38-bit to accommodate 1-second of statistic counts)
    • Byte count
    • Frame count
    • PAUSE frame count
    • Multicast frame count
    • Unicast frame count
    • Undersize frame count
    • Oversize frame count
    • Frame count statistic for the following sized frames:
      • 64
      • 65-127
      • 128-255
      • 256-511
      • 512-1023
      • 1024-1518
      • 1519-1522
      • 1523-1548
      • 1549-2047
      • 2048-4095
      • 4096-8191
      • 8192-9215
      • > 9215
    • RX FCS check and removal
    • RX PAUSE frame processing and handling
    • RX Performance Monitoring and Statistics (counters are 38-bit to accommodate 1-second of statistic counts)
      • Bad FCS
      • Bad Preamble
      • Byte count
      • Frame count
      • PAUSE frame count
      • Multicast frame count
      • Unicast frame count
      • Bad FCS frame count
      • Bad byte count
      • Bad frame count
      • Bad aligned frame count
      • Jabber frame count
      • Runt frame count
      • Undersize frame count
      • Oversize frame count
      • Frame count statistic for the following sized frames:
        • 64 byte
        • 65-127
        • 128-255
        • 256-511
        • 512-1023
        • 1024-1518
        • 1519-1522
        • 1523-1548
        • 1549-2047
        • 2048-4095
        • 4096-8191
        • 8192-9215
        • > 9215

    Additional Add-on features

    • HiGig, HiGig+ and HiGig-lite
    • 1588v2, OAM, OWAMP, TWAMP time stamping 1-step and 2-step
    • xGFC/FlexE/OTN/FlexO/OTU25/50-RS access port
    • FC1200 to 256GFC FC2 Monitoring
    • 802.1Qbb Priority Flow Control (PFC) up to 8 priorities
    • 802.3br Express Traffic

Cell Area : call for detail

Gate count : call for detail

TX/RX round trip latency from MAC User Interface: call for detail

  • Specially designed for telecom application and service provider ASICs
  • OTN mapping ports
  • FlexE access ports
  • FlexO, OTU25 and OTU50 framing and access ports
  • Multiple level timestamp and UDP checksum update
  • High precision timestamp accuracy
  • Feature-rich SW programmability
  • Multiple MAC client access ports