SoftIP IP Group of Alphawave IP
SoftIP IP Group of Alphawave IP

100G OTN Transponder with AES


Precise-ITC offers a dynamically reconfigurable Nx100GE multi-lane OTN (Callite) transponder SOC solution for 100GE or generic CBR clients. The Nx100G SOC is a single chip multi-lane solution for CBR clients via GMP mapping or for packet client via GFP-F mapping. For packet/GFP-F mapping, oversubscription is supported with bandwidth buffer.

AES-GCM encryption and MAC/RS statistics and performance monitoring are optional add-on features to further enhance the power of Callite SOC.

Each lane is individually configurable through an easy to use Software Application Programming Interface (API)/Customizable software driver.

Figure 1 : Callite Transponder Lane Core Block Diagram

  • Line Interface
    • OTU4+G.709 GFEC
    • OTL4.10 or OTL4.4 (with flexible deskew buffers)
  • Client Interface
    • 100G Ethernet (IEEE 802.3ba + 802.3bj FEC)
    • 100G CBR clients
    • 100GBASE-R or CAUI/CAUI4
    • SFI-S (CBR client)
  • Ethernet Media Access Control (MAC) + RS Link ( Optional )
    • Ethernet frame delineation adhering to 802.3
    • Statistics gathering
  • AES-GCM Encryption at OPU layer ( Optional )
    • 100G OPU4 layer bulk encryption using AES-GCM
    • Programmable encryption message size, dedicated SW key-exchange/messaging via ODU OH, NIST/FIPS compliance AES algorithm
  • GFP-F Encapsulation and Delineation
    • Compliant to G.7041
    • Provides optional IDLE insertion and removal
    • Support oversubscription with elastic packet buffer
  • Generic Mapping Procedure (GMP)
    • Client Signal mapping/de-mapping and rate adaption to/from OPU4
    • Compliant with G.709
  • OTN Mapper +GFEC
    • Maps GMP mapped or GFP encapsulated payload to OPU4
    • OPU/ODU/OTU Overhead generation including alarms. OH fields programmed through software registers or via an OH insertion interface.
    • 709 GFEC generation
    • Optional using external proprietary FEC encoding
  • OTN De-mapper +GFEC
    • ODU/OTU frame alignment with programmable FAS
    • ODU/OTU overhead processing including detection of faults
    • OTU/ODU/OPU overhead monitoring. Capture of registers for software processing of slow changing fields or option to send to an OH extraction interface for processing by an external device.
    • 709 GFEC decode processing
    • Optional using external proprietary FEC decoding
  • Processor Interface
    • Simple request-acknowledge register access to 32-bit registers for device configuration and statistic collection.
    • Optional AXI4-lite interface
  • Application Programming Interface
    • Complete API for ease of use for configuration, error processing and monitoring.


Callite is a multi-lane SOC solution to transpond 100GE or CBR100G client onto Optical Transport Network (OTN).  Each lane can be configured independently. Each lane core supports mapping of CBR100G client and 100GE client. For 100GE client, the core can perform constant bit-rate (CBR) async mapping using GMP or packet mapping using GFP. With packet mapping, a bandwidth buffer is used for bandwidth management between the GFP mapper and the 100GE MAC.

The OTU4 core of Callite supports 3 levels of OH insertions and extractions : register programming, memory programming and external programming via a dedicated OH port. The gFEC function can be disabled (or removed to save area) and a custom high-gain FEC can be used. The OTU4 core supports full alarm and OH inserts and extracts as specified in ITU G.709 and ITU G.798.


The following shows a few examples of how the transponder can be configured for different applications:

  • 100GBASE-R <> CAUI/CAUI4 <> Ethernet Mac <> GFP-F <> OPU/ODU4 <> OTU4+GFEC <> OTL4.4/OTL4.10
  • 100GBASE-R <> CAUI/CAUI4 PCS-R/MLD <> GMP <> OPU/ODU4 <> OTU4+GFEC <> OTL4.4/OTL4.10
  • 100G CBR <> SFI-S <> GMP <> OPU/ODU4 <> OTU4+GFEC <> OTL4.4/OTL4.10

Each lane is independent and can be dynamically re-configured to perform a different function without affecting the other lanes in mission.

Our SOC solution can offer much higher lane (port) density per chip, typically 1-4 depending on ASIC/FPGA sizes. As a result of higher port density, better power efficiency and cost effectiveness can be obtained.

Standard Compliance

ITU-T REC-G.709/Y.1331-02/2012
ITU-T REC-G.709/Y.1331-10/2012-Cor1
ITU-T REC-G.709/Y.1331-10/2013-Amd2
ITU-T REC-G.798-12/2012
ITU-T REC-G.798.1-01/2013
IEEE 802.3-2012
IEEE 802.3bj