Flexible evaluation vehicle incorporates eSilicon 112 Gbps SerDes
May 01, 2019 02:00 ET | Source: eSilicon Corporation
SAN JOSE, Calif., May 01, 2019 (GLOBE NEWSWIRE) — eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the tapeout of a 7nm test ASIC that supports 400G gearbox and retimer functionality. A gearbox converts multiple serial data streams at one rate to multiple streams at another rate. Serial-to-parallel and parallel-to-serial converters (SerDes) are critical to this functionality. A retimer improves signal integrity by equalizing, retiming and re-conditioning the received data to extend reach.
The test ASIC includes four lanes of eSilicon’s long-reach 112 Gbps SerDes and eight lanes of its long-reach 56 Gbps SerDes. The eSilicon SerDes IP is integrated with media access control (MAC), forward error correction (FEC) and gearbox IP from Precise-ITC. The test ASIC is designed to allow customers to evaluate eSilicon’s SerDes IP and the Precise E-pak Ethernet IP in a test vehicle that is representative of a real-life application. It features long reach and low power as well as low latency for time-critical applications, such as high-performance computing. The technology in the chip can be used as the basis for developing 400G and 800G systems.
“This new test ASIC will open up new opportunities for our customers,” said Hugh Durdan, vice president, strategy and products at eSilicon. “We employed the latest release of our StarDesignerä 7nm flow for this design. Thanks to the global, early analysis of integration challenges delivered by the flow, we were able to meet all performance parameters for this design and tape out on schedule.”
“Precise-ITC is a leading provider of Ethernet and Optical Transport Network (OTN) intellectual property products for ASIC and FPGA,” said Silas Li, director of engineering at Precise-ITC. “We’re delighted to showcase our industry leading IP in eSilicon’s advanced ASIC flow.”
The 7nm gearbox/retimer test ASIC will be out of fabrication in September, 2019. eSilicon will announce silicon measurement data and availability at that time.
To learn more about eSilicon’s StarDesigner flow, visit eSilicon’s How We Do It page. You can learn more about eSilicon’s 7nm IP platform here, or contact your eSilicon sales representative directly or via email@example.com. You can learn more about the Precise-ITC 400G Ethernet Core here.
About eSiliconeSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets. www.esilicon.com
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