Ethernet Controller IP Division of Alphawave IP
Ethernet Controller IP Division of Alphawave IP

50GE : PCS+FEC (802.3cd) Core

The Precise-ITC 50G PCS+FEC IP cores implement and compliance with the PCS-R, RS-FEC Sublayer for 50GBASE-R function based on the IEEE 802.3cd (DRAFT-3.x). The RS-FEC algorithm is also known as KP4 FEC RS(544,514).

The 50GE PCS+FEC Core maps the incoming 50GMII signal to 64B/66B, then inserted with AM inserted PCS signal for transmission, 256/257B transcoding, FEC calculation, and data distribution to support multiple lanes in the Physical Layer.  This core is suitable for use in switch or interface cards or any application that requires a RS-FEC for 50GbE. All functions of the 50GFEC are compliant with the IEEE 802.3cd/D-TBD.  For a complete Ethernet solution, the 50G PCS+FEC seamlessly integrates with the Precise-ITC 50G MAC(50GMAC) core.




  • PCS encoding on 50GMII ++
  • AM insertion ++
  • AM removal of incoming 66B encoded PCS (with AM) signal ++
  • 256/257B transcoding (to reduce overhead for FEC insertion)
  • Alignment Marker (AM) insertion. Unique marker portion of AM for each lane is s/w configurable.
  • Forward Error Correction (FEC) parity calculation and insertion
  • Symbol Distribution so that output is composed of 2 lanes of 80-bits each
  • Bitmux for 56G serdes
  • Clause 45 MDIO register set
  • Error detection and interrupt reporting


  • Bit-demux for 56G serdes
  • Alignment lock and lane deskew of 2 lanes. Unique marker portion of AM for each lane is SW configurable
  • Lane reordering
  • FEC decoding and error correction
  • Alignment marker removal
  • Reverse 256/257B transcoding
  • AM insertion ++
  • AM removal ++
  • 66B decoding ++
  • Error detection and interrupt reporting
  • Loopback from TX 50GPCS to RX 50GPCS
  • Performance Monitoring and Statistics
    • Dynamic skew measurement for each lane
    • FEC Corrected code word count
    • FEC Uncorrected code word count
    • FEC symbol error counter
    • PCS Status – link up/down
    • High bit error rate (hi-BER)
    • FEC degraded SER
    • BER counter
    • Multi-lane AM status (locked and aligned/not locked and aligned)
    • Lane mapping for each of physical lanes 0-1

++ If PCS and FEC layer are combined, these redundant functions are removed.