SoftIP IP Group of Alphawave IP
SoftIP IP Group of Alphawave IP

Junior / Intermediate ASIC_FPGA Engineer

Job Title:  Junior / Intermediate ASIC_FPGA Engineer

Precise-ITC Incorporated is a complete ASIC and FPGA solutions provider.  We provide professional consulting services as well as intellectual property (IP) development, with a focus on telecommunications.  But there’s more – custom design, tailored for each customer, and system on a chip development is our specialty!

Expert in FPGA and ASIC design and verification, we excel at finding innovative solutions for our customers to fit their time and budgetary requirements.

Conveniently located in Ottawa – the heart of Silicon Valley North, Precise-ITC has been proudly serving the industry since 2003.

Job Description:

The candidate must have a minimum of 1 year of experience in FPGA or ASIC development which must include both design and verification. The candidate will work within a team responsible for the development of OTN / Ethernet Intellectual Property (IP) with the responsibility of both RTL design and verification.

Job Duties:

  • Work within a team of engineers to deliver standards-compliant IP blocks for use in OTN / Ethernet FPGAs or ASICs.
  • Develop and document the design using Verilog
  • Develop and document the verification environment using SystemVerilog + UVM
  • Develop and execute individual test-cases against the RTL
  • Issue and track bug reports from inception to closure
  • Mentor junior engineers

Must comprehensively possess the following skills

  • Telecommunications Protocol knowledge (OTN, Sonet, Ethernet, etc)
  • Verilog
  • FPGA compilation tools
  • SystemVerilog+UVM
  • Randomized and Directed Verification Methodologies
  • Unix/Linux Shell scripting
  • Source code revisioning systems, SVN, CVS, RCS e.g.
  • Demonstrated verbal and written communications skills
  • Ability to mentor junior engineers
  • Ability to independently execute on a project while working well with others in the group

Useful knowledge to have

  • OTN transport systems
  • Debugging Tools
  • PERL, TCL, Python, and C/C++ programming

Education and Experience

  • MSEE with 1 year of experience or BSEE with 2 years of experience in ASIC or FPGA development

Please email us at Note: Only selected candidates will be contacted.