800GE BASE-R PCS Core Features
- PCS layer formed by bonded 2x 400GE PCS in PCS Layer
- Using only 8 virtual logical lanes based on 2 x 16 logical lanes of 400GE PCS to reduce power in 800G operation
- Well designed into using 112G/s Serdes to provide highest port density for 800G Ethernet solution.
400G/200G/100G/50G/40G/25G/10G BASE-R PCS Core Features
PCS TX Core
- 256/257B transcoding (to reduce overhead for FEC insertion) (not applicable for 10GE)
- X58 Scrambling (optional bypass) (not applicable for 10GE)
- 64B/66B encoding of incoming MII signal
- Idle block removal (to reduce overhead for AM insertion)
- Alignment Marker (AM) insertion. Unique marker portion of AM for each lane is s/w configurable.
- Test pattern generation (scrambled idles)
- Clause 45 MDIO register set
- Error detection and interrupt reporting
Specific Feature for 800GBASE-R/400GBASE-KP4/200GBASE-KP4/100GBASE-KP/50GBASE-KP
- KP4 (RS544,514) Forward Error Correction (FEC) parity calculation and with symbol distribution
Specific Feature for 100GBASE-KR4/CR4 and 25GBASE-KR
- KR4 (RS528,514) Forward Error Correction (FEC) parity calculation and insertion with symbol distribution
PCS RX Core
- 64B/66B decoding to MII signal
- Reverse 256/257B transcoding (not applicable to 10GE)
- X58 De-scrambling (optional bypass) (not applicable for 10GE)
- Alignment marker removal (where applicable)
- Unique marker portion of AM for each lane is s/w configurable (where applicable)
- Test pattern monitoring
- Clause 45 MDIO register set
- Error detection and interrupt reporting
- Loopback from TX MII to RX MII
- Performance Monitoring and Statistics
- Dynamic skew measurement for each lane
- PCS Status – link up/down
- High bit error rate (hi-BER)
- BER counter
- Test pattern error counter
- Multi-lane AM status (locked and aligned/not locked and aligned)
- FEC Corrected code word count (with FEC enabled)
- FEC corrected 1s and 0s counts
- FEC symbol error histogram for KP and KR FEC
- FEC Uncorrected code word counts
- FEC symbol error counters
- FEC degrade SER
- FEC Hi-SER alarm
Specific Feature for 800GBASE-R/400GBASE-KP4/200GBASE-KP4/100GBASE-KP/50GBASE-KP
- Alignment lock and lane deskew
- Lane reordering
- KP4 (RS544,514) FEC decoding and error correction
Specific Feature for 100GBASE-KR4/CR4 and 25GBASE-KR
- Alignment lock and lane deskew
- KR4 (RS528,514) FEC decoding and correction
800G/400G/200G/100G/50G/40G/25G/10G MAC Core Features (per channel)
- TX FCS insertion
- TX MAC control frame generation
- Unicast/Multicast PAUSE frame generation by MAC client or by software
- Software configurable PAUSE quanta
- TX Performance Monitoring and Statistics (counters are 38-bit to accommodate 1-second of statistic counts)
- Byte count
- Frame count
- PAUSE frame count
- Multicast frame count
- Unicast frame count
- Undersize frame count
- Oversize frame count
- Frame count statistic for the following sized frames:
- 64
- 65-127
- 128-255
- 256-511
- 512-1023
- 1024-1518
- 1519-1522
- 1523-1548
- 1549-2047
- 2048-4095
- 4096-8191
- 8192-9215
- > 9215
- RX FCS check and removal
- RX PAUSE frame processing and handling
- RX Performance Monitoring and Statistics (counters are 38-bit to accommodate 1-second of statistic counts)
- Bad FCS
- Bad Preamble
- Byte count
- Frame count
- PAUSE frame count
- Multicast frame count
- Unicast frame count
- Bad FCS frame count
- Bad frame count
- Bad aligned frame count
- Undersize frame count
- Oversize frame count
- Frame count statistic for the following sized frames:
- 64 byte
- 65-127
- 128-255
- 256-511
- 512-1023
- 1024-1518
- 1519-1522
- 1523-1548
- 1549-2047
- 2048-4095
- 4096-8191
- 8192-9215
- > 9215
Additional Add-on features
- 1588v2 time stamping
- 802.3br Express Traffic
- 802.1Qbb Priority Flow Control (PFC) up to 8 priorities