MCMR 800GE (E-pak 800G IP)

EN/

Multi-channel Multi-rate 800G Ethernet Package – E-pak 800G IP Core

The E-pak SOC Core from Precise-ITC is a multi-rate Ethernet aggregator that supports tributaries from 800GE, to 1GE. E-pak 800G is our 3rd generation of E-pak solution utilizing the 112G/s serdes and 56G/s serdes.

Ultra low latency : 800G MAC+PCS+FEC (round-trip) < 74 ns.

The supported ethernet protocols are 800GE, 400GE, 200GE, 100GE, 50GE, 40GE, 25GE, 10GE and 1GE. It supports any legal combination of ethernet rate up to 800G. This Core supports up to a maximum of 8 ethernet channel and works most effective and efficient with latest 112G/s serdes. With Core clock frequency of 1.6GHz at 7nm, this Core delivers smallest footprint among similar solution in the Ethernet SOC market.

800GE Support

The Core supports 800GE which uses a full 800GE MAC and a pair of “bonded” 2 x 400GE PCS. The 800GE takes advantage of 112G/s serdes and uses 8 or 16 virtual logical lanes in a “bonded” 2 x 400GE PCS. This improves power efficiency in 800G operation.

Overview

The north-bound interface from the multi-channel MAC provides a configurable system interface. The Multi-channel MAC manages the mapping between individual MACs and the assigned I/O or I/O group.

The southbound interface is mapped (at the PMA layer) to the on-chip SERDES. The core is responsible for channel alignment and FEC (where applicable).

Benefits

  • Combines Ethernet streams at a variety of rates to a single multi-channel interface at the MAC
  • The E-pak800 allows access connections supporting 1GE, 10GE, 25GE, 40GE, 50GE, 100GE, 200GE, 400GE and 800GE in any combination on any port or groups of ports to a maximum total bandwidth of 800Gbps
  • Dynamically change rate on any port without affecting existing traffic
  • Pre-standard 800GE supports with bonded 2 x 400GE PCS and a single 800G MAC
  • Fully utilize the advantages of 112G serdes to get highest possible port density per 800G.
  • Ultra low latency and power efficient FEC engine
  • Support 1588, 802.1Qbb (PFC) and 802.3br express traffic (TSN).

Table 1: Example Configurations of PCS core

PCS Channel Type Num Channel(s)
with 16 x 56G NRZ Serdes
Num Channel(s)
with 8 x 112G PAM4 Serdes
KP4 FEC KR4 FEC FC FEC No FEC
800GBASE-R8   1        
800GBASE-R16 1          
400GBASE-R16  1   X      
400GBASE-R8 2   X      
400GBASE-R4 2 X      
200GBASE-R8  2  1 X      
200GBASE-R4 4 2 X      
200GBASE-R2 4 X      
100GBASE-R4  4 X X   X
100GBASE-R2 8 4 X      
100GBASE-R1   8 X      
50GBASE-R4 4 2       X
50GBASE-R2 8 4 X X    
50GBASE-R1 16 8 X      
40GBASE-R4 4 2     X X
25GBASE-R1 16 8   X X X
10GBASE-R 16 8     X X
1GBASE-X / SGMII / 100M /10M 16 8       X

Applications

  • High-density routers for data centers
  • Access switches

800GE BASE-R PCS Core Features

  • PCS layer formed by bonded 2x 400GE PCS in PCS Layer
  • Using only 8 or 16 virtual logical lanes based on 400GE PCS to reduce power in 800G operation
  • Well designed into using 56G/s and 112G/s Serdes to provide highest port density for 800G Ethernet solution.

400G/200G/100G/50G/40G/25G/10G BASE-R PCS Core Features

PCS TX Core

  • 256/257B transcoding (to reduce overhead for FEC insertion) (not applicable for 10GE)
  • X58 Scrambling (optional bypass) (not applicable for 10GE)
  • 64B/66B encoding of incoming MII signal
  • Idle block removal (to reduce overhead for AM insertion)
  • Alignment Marker (AM) insertion.  Unique marker portion of AM for each lane is s/w configurable.
  • Test pattern generation (scrambled idles)
  • Clause 45 MDIO register set
  • Error detection and interrupt reporting

Specific Feature for 800GBASE-R/400GBASE-KP4/200GBASE-KP4/100GBASE-KP/50GBASE-KP

  • KP4 (RS544,514) Forward Error Correction (FEC) parity calculation and with symbol distribution

Specific Feature for 100GBASE-KR4/CR4 and 25GBASE-KR

  • KR4 (RS528,514) Forward Error Correction (FEC) parity calculation and insertion with symbol distribution

PCS RX Core

  • 64B/66B decoding to MII signal
  • Reverse 256/257B transcoding (not applicable to 10GE)
  • X58 De-scrambling (optional bypass) (not applicable for 10GE)
  • Alignment marker removal (where applicable)
  • Unique marker portion of AM for each lane is s/w configurable (where applicable)
  • Test pattern monitoring
  • Clause 45 MDIO register set
  • Error detection and interrupt reporting
  • Loopback from TX MII to RX MII
  • Performance Monitoring and Statistics
    • Dynamic skew measurement for each lane
    • PCS Status – link up/down
    • High bit error rate (hi-BER)
    • BER counter
    • Test pattern error counter
    • Multi-lane AM status (locked and aligned/not locked and aligned)
    • FEC Corrected code word count (with FEC enabled)
    • FEC corrected 1s and 0s counts
    • FEC symbol error histogram for KP and KR FEC
    • FEC Uncorrected code word counts
    • FEC symbol error counters
    • FEC degrade SER
    • FEC Hi-SER alarm

Specific Feature for 800GBASE-R/400GBASE-KP4/200GBASE-KP4/100GBASE-KP/50GBASE-KP

  • Alignment lock and lane deskew
  • Lane reordering
  • KP4 (RS544,514) FEC decoding and error correction

Specific Feature for 100GBASE-KR4/CR4 and 25GBASE-KR

  • Alignment lock and lane deskew
  • KR4 (RS528,514) FEC decoding and correction

800G/400G/200G/100G/50G/40G/25G/10G MAC Core Features (per channel)

  • TX FCS insertion
  • TX MAC control frame generation
    • Unicast/Multicast PAUSE frame generation by MAC client or by software
    • Software configurable PAUSE quanta
  • TX Performance Monitoring and Statistics (counters are 38-bit to accommodate 1-second of statistic counts)
    • Byte count
    • Frame count
    • PAUSE frame count
    • Multicast frame count
    • Unicast frame count
    • Undersize frame count
    • Oversize frame count
    • Frame count statistic for the following sized frames:
      • 64
      • 65-127
      • 128-255
      • 256-511
      • 512-1023
      • 1024-1518
      • 1519-1522
      • 1523-1548
      • 1549-2047
      • 2048-4095
      • 4096-8191
      • 8192-9215
      • > 9215
  • RX FCS check and removal
  • RX PAUSE frame processing and handling
  • RX Performance Monitoring and Statistics (counters are 38-bit to accommodate 1-second of statistic counts)
    • Bad FCS
    • Bad Preamble
    • Byte count
    • Frame count
    • PAUSE frame count
    • Multicast frame count
    • Unicast frame count
    • Bad FCS frame count
    • Bad frame count
    • Bad aligned frame count
    • Undersize frame count
    • Oversize frame count
    • Frame count statistic for the following sized frames:
      • 64 byte
      • 65-127
      • 128-255
      • 256-511
      • 512-1023
      • 1024-1518
      • 1519-1522
      • 1523-1548
      • 1549-2047
      • 2048-4095
      • 4096-8191
      • 8192-9215
      • > 9215

Additional Add-on features

  • 1588v2, OAM, OWAMP, TWAMP 1-step and 2-step time stamping
  • OTN/FlexO access port
  • 802.1Qbb Priority Flow Control (PFC) up to 8 priorities

AREA and Latency (Estimated) :

Cell Area : call for detail

Gate count : call for detail

TX/RX round trip latency from MAC User Interface : < 74 ns