Canada Technology Innovation – ASIC, FPGA & Embedded Software !
Canada Technology Innovation – ASIC, FPGA & Embedded Software !

MCMR 1.6T (E-pak 1p6T IP)

EN/

Multi-channel Multi-rate 1.6T Ethernet Package (E-pak 1p6T IP Core)

The E-pak SOC Core from Precise-ITC is a multi-rate Ethernet aggregator that supports tributaries from 800GE, to 1GE. E-pak 1.6T is our 5th generation of E-pak solution utilizing the 112G/s serdes and 56G/s serdes. The SOC consists of Epak 1p6T MC PCS and Epak 1p6T MC MAC Core.

The supported ethernet protocols are 800GE, 400GE, 200GE, 100GE, 50GE, 40GE, 25GE, 10GE and 1GE. It supports any legal combination of ethernet rate up to 800G. This Core supports up to a maximum of 8 ethernet channel and works most effective and efficient with latest 112G/s serdes. With Core clock frequency of 670MHz to 1.6GHz at 7nm or 5nm, this Core delivers smallest footprint among similar solution in the Ethernet SOC market.

800GE Support

The Core supports 800GE which uses a full 800GE MAC and a pair of “bonded” 2 x 400GE PCS. The 800GE takes advantage of 112G/s serdes and uses virtual logical lanes in a “bonded” 2 x 400GE PCS. This improves power efficiency in 800G operation. The 800GE is compliant to the Ethernet Technology Consortium Standard.

Overview

The north-bound interface from the multi-channel MAC provides a configurable system interface. The Multi-channel MAC manages the mapping between individual MACs and the assigned I/O or I/O group.

The southbound interface is mapped (at the PMA layer) to the on-chip SERDES. The core is responsible for channel alignment and FEC (where applicable).

This image has an empty alt attribute; its file name is 800g.png

Benefits

  • Digital Crossbar among all serdes lanes in both TX and RX direction in the serdes Mux/Demux
  • Combines Ethernet streams at a variety of rates to a single multi-channel interface at the MAC
  • The E-pak1p6T allows access connections supporting 1GE*, 10GE, 25GE, 40GE, 50GE, 100GE, 200GE, 400GE and 800GE in any combination on any port or groups of ports to a maximum total bandwidth of 1.6Tbps
  • Support IEEE 802.3 required FEC variances – LL FEC RS(272, 258), KR4 FEC RS528,514, KP4 FEC RS544,514, FC FEC (2112,2080)
  • Support HiGig, HiGig+ and HiGig-lite
  • Dynamically change rate on any port without affecting existing traffic
  • Standard ETC 800GE supports with bonded 2 x 400GE PCS and a single 800G MAC
  • Fully utilize the advantages of 112G serdes to get highest possible port density per 800G.
  • Provide OTN, FlexE, FlexO, OTU25/50-RS, xGFC access ports (Optional add-on)
  • Optional10GFC to 256GFC Monitoring
  • Ultralow latency and power efficient FEC Core
  • Support 1588, 802.1Qbb (PFC) and 802.3br express traffic (TSN).

Applications

  • High-density routers for data centers
  • Access switches
PCS Channel TypeNum Channel(s)
with 16 x 112G Serdes Config
KP4 FECKR4 FECFC FECNo FEC
800GBASE-R82    
800GBASE-R161    
400GBASE-R161X   
400GBASE-R82X   
400GBASE-R44X   
200GBASE-R8 2X   
200GBASE-R44X   
200GBASE-R28X   
100GBASE-R4XX X
100GBASE-R28X   
100GBASE-R116X   
50GBASE-R44   X
50GBASE-R28XX  
50GBASE-R116X   
40GBASE-R44  XX
25GBASE-R116 XXX
10GBASE-R16  XX
1GBASE-X / SGMII / 100M /10M16   X

800GE BASE-R PCS Core Features

  • PCS layer formed by bonded 2x 400GE PCS in PCS Layer
  • Using 32 virtual logical lanes based on 2 x 400GE PCS to reduce power in 800G operation
  • Well designed into using 112G/s Serdes to provide highest port density for 800G Ethernet solution.

400G/200G/100G/50G/40G/25G/10G BASE-R PCS Core Features

PCS TX Core

  • 256/257B transcoding (to reduce overhead for FEC insertion) (not applicable for 10GE)
  • X58 Scrambling (optional bypass) (not applicable for 10GE)
  • 64B/66B encoding of incoming MII signal
  • Idle block removal (to reduce overhead for AM insertion)
  • Alignment Marker (AM) insertion.  Unique marker portion of AM for each lane is s/w configurable.
  • Test pattern generation (scrambled idles)
  • Clause 45 MDIO register set
  • Error detection and interrupt reporting

Specific KP4 FEC Feature for 800GBASE-R/400GBASE-KP4/200GBASE-KP4/100GBASE-KP/50GBASE-KP

  • KP4 (RS544,514) Forward Error Correction (FEC) parity calculation and with symbol distribution

Specific KR4 FEC Feature for 100GBASE-KR4/CR4, 50GBASE-KR2 and 25GBASE-KR

  • KR4 (RS528,514) Forward Error Correction (FEC) parity calculation and insertion with symbol distribution

Specific FC FEC Feature for 50GBASE-R4, 40GBASE-R, 25GBASE-R and 10GBASE-R

  • RS (2112,2080) Forward Error Correction (FEC) parity calculation and insertion

PCS RX Core

  • 64B/66B decoding to MII signal
  • Reverse 256/257B transcoding (not applicable to 10GE)
  • X58 De-scrambling (optional bypass) (not applicable for 10GE)
  • Alignment marker removal (where applicable)
  • Unique marker portion of AM for each lane is s/w configurable (where applicable)
  • Test pattern monitoring
  • Clause 45 MDIO register set
  • Error detection and interrupt reporting
  • Loopback from TX MII to RX MII
  • Performance Monitoring and Statistics
    • Dynamic skew measurement for each lane
    • PCS Status – link up/down
    • High bit error rate (hi-BER)
    • BER counter
    • Test pattern error counter
    • Multi-lane AM status (locked and aligned/not locked and aligned)
    • FEC Corrected code word count (with FEC enabled)
    • FEC corrected 1s and 0s counts
    • FEC symbol error histogram for KP and KR FEC and FC FEC
    • FEC Uncorrected code word counts
    • FEC symbol error counters
    • FEC degrade SER
    • FEC Hi-SER alarm

Specific KP4 FEC Feature for 800GBASE-R/400GBASE-KP4/200GBASE-KP4/100GBASE-KP/50GBASE-KP

  • Alignment lock and lane deskew
  • Lane reordering
  • KP4 (RS544,514) FEC decoding and error correction

Specific KR4 FEC Feature for 100GBASE-KR4/CR4, 50GBASE-KR2 and 25GBASE-KR

  • Alignment lock and lane deskew
  • KR4 (RS528,514) FEC decoding and correction

Specific FC FEC Feature for 50GBASE-R4, 40GBASE-R, 25GBASE-R and 10GBASE-R

  • Alignment sync
  • FC FEC (RS2112,2080) FEC decoding and correction

800G/400G/200G/100G/50G/40G/25G/10G MAC Core Features (per channel)

  • TX FCS insertion
  • TX MAC control frame generation
    • Unicast/Multicast PAUSE frame generation by MAC client or by software
    • Software configurable PAUSE quanta
  • TX Performance Monitoring and Statistics (counters are 38-bit to accommodate 1-second of statistic counts)
    • Byte count
    • Frame count
    • PAUSE frame count
    • Multicast frame count
    • Unicast frame count
    • Undersize frame count
    • Oversize frame count
    • Frame count statistic for the following sized frames:
      • 64
      • 65-127
      • 128-255
      • 256-511
      • 512-1023
      • 1024-1518
      • 1519-1522
      • 1523-1548
      • 1549-2047
      • 2048-4095
      • 4096-8191
      • 8192-9215
      • > 9215
  • RX FCS check and removal
  • RX PAUSE frame processing and handling
  • RX Performance Monitoring and Statistics (counters are 38-bit to accommodate 1-second of statistic counts)
    • Bad FCS
    • Bad Preamble
    • Byte count
    • Frame count
    • PAUSE frame count
    • Multicast frame count
    • Unicast frame count
    • Bad FCS frame count
    • Bad byte count
    • Bad frame count
    • Bad aligned frame count
    • Jabber frame count
    • Runt frame count
    • Undersize frame count
    • Oversize frame count
    • Frame count statistic for the following sized frames:
      • 64 byte
      • 65-127
      • 128-255
      • 256-511
      • 512-1023
      • 1024-1518
      • 1519-1522
      • 1523-1548
      • 1549-2047
      • 2048-4095
      • 4096-8191
      • 8192-9215
      • 9215

Additional Add-on features

  • HiGig, HiGig+ and HiGig-lite
  • 1588v2, OAM, OWAMP, TWAMP time stamping 1-step and 2-step
  • xGFC/FlexE/OTN/FlexO /OTU25/50-RS access port
  • 10GFC to 256GFC Monitoring
  • 802.1Qbb Priority Flow Control (PFC) up to 8 priorities
  • 802.3br Express Traffic

AREA and Latency (Estimated):

Typical configuration

Cell Area : call

Gate count : call

TX/RX round trip latency from MAC User Interface :  call

Telco Edition:

  • Specially designed for telecom application and service provider ASICs
  • OTN mapping ports
  • FlexE access ports
  • FlexO, OTU25 and OTU50 framing and access ports
  • Multiple level timestamp and UDP checksum update
  • High precision timestamp accuracy
  • Feature-rich SW programmability
  • Multiple MAC client access ports