SoftIP IP Group of Alphawave IP
SoftIP IP Group of Alphawave IP

ASIC Turnkey Services

We can help in all area of ASIC flow from idea and concept to final GDSII tapeout. Here is a brief outline of the services that we can provide. And this is just the tip of the iceberg!

  • Architecture and concept
  • ASIC flow/environment setup
  • ASIC and verification services (front-end)
    • RTL coding
    • SystemVerilog UVM verification
  • Custom IP development & verification
  • Design re-optimization
  • ASIC Synthesis, DFT, STA, Formal Verification, ATPG
  • ASIC Physical Design (Layout – back-end)
  • Production Test Generation and Consulting

Planning and Evaluation Phase

  • ASIC project – feasibility study
  • Technology evaluation
  • Project planning and management
  • Software API and driver

Design & Functional Verification Phase

  • ASIC functional description and architecture
  • Digital (RTL) design using Verilog/VHDL
  • System and module verification using SystemVerilog UVMCapture-microchip-bottom
  • Mixed-signal SoC or Digital SoC integration
  • Design-for-test (DFT) insertion and verification
  • DFT (ATPG) test vector generation
  • Static Timing Analysis (STA)
  • Formal Verification
  • Physical Design, ECO and timing closures

Production Phase

  • Functional vector generation
  • ATPG vector generation
  • Test planning and production flow
  • Deployment firmware development
  • Test board (for tester)
  • Evaluation board / Reference design PCB
  • Application engineering support
  • Customer Solutions – user interface, evaluation kits and so on.

CAD and Development Tools

  • Cadence IUS – functional simulation using SystemVerilog UVM
  • Synopsys – synthesis, DFT, STA, ATPG and physical design
  • High-performance server farm

Note : * After design and layout phase, we will handle and manage all fabrication, packaging and testing services through our partners.