10G/25GBASE-R PCS+ KR4 FEC IP Core

EN/

10G/25Gbps Ethernet PCS, KR4 FEC and MAC IP Core

The fully integrated Physical Coding Sublayer (PCS), KR4 FEC and Media Access Controller (MAC) core for 25Gbps Ethernet applications are compliant with IEEE 802.3by standard. The interface to the PMA supports a single 10G/25Gbps bi-directional, serial interface. The PCS sublayer includes 66B encoding, transcoding, and scrambling. This Core also supports CPRI-8, 9 and 10 PCS mode configurable through software register.

The north-bound interface from the MAC provides a configurable 64-bit system interface.

The southbound interface performs the mapping of transmitting and receiving data streams (at the PMA layer) to the on-chip SERDES.

Benefits

  • Proven IP reduces development time and risk
  • Upgrade process as the standard evolves
  • Supports both 10G/25GBASE-R PMD interfaces
  • Support next-generation 25G NRZ SerDes
  • Support for a single-lane SERDES interface Optional KR4 FEC (528,514) RS FEC integration
  • Optional CPRI-8, 9 & 10 PCS Mode support
  • Off-the-shelf, proven technology implementation in FPGAs and ASIC SOC
  • Tested and interoperability-proven against Spirent and Viavi test equipment

Features

  • Integrated MAC and PCS for area efficiency
  • Fully compatible with IEEE802.3 2015 and IEEE 802.3by-2016 Standards
  • Super low latency with minimized fixed and variable delay for network efficiency.
  • Supports 1588v2 time stamps and full error handling
  • Supports 802.3br express traffic and 802.1Qbb priority flow control (PFC)

Applications

  • High-performance server network interface cards
  • Mid-sized routers

10G/25GBASE-R PCS Core Features

PCS TX Core

  • 64B/66B encoding of incoming MII signal
  • X58 Scrambling (optional bypass)
  • Test pattern generation
  • Clause 45 MDIO register set

 

PCS RX Core

  • 64B/66B decoding to MII signal
  • Test pattern monitoring
  • Clause 45 MDIO register set
  • Error detection and interrupt reporting
  • Loopback from TX MII to RX MII
  • Performance Monitoring and Statistics
    • PCS Status – link up/down
    • High bit error rate (hi-BER)
    • BER counter
    • Test pattern error counter

25GE KR4 FEC (Optional) Features

TX path

  • 256/257B transcoding
  • Alignment Marker (AM) insertion. Unique marker portion of AM for each lane is s/w configurable.
  • KR4 (RS528,514) Forward Error Correction (FEC) parity calculation and insertion with symbol distribution
  • Test pattern generation (scrambled idles)
  • Clause 45 MDIO register set
  • Error detection and interrupt reporting

RX path

  • Reverse 256/257B transcoding
  • Alignment marker removal
  • Unique marker portion of AM for each lane is s/w configurable
  • Test pattern monitoring
  • Alignment lock
  • KR4 (RS528,514) FEC decoding and correction
  • Performance Monitoring and Statistics
    • Dynamic skew measurement for each lane
    • PCS Status – link up/down
    • High bit error rate (hi-BER)
    • BER counter
    • Test pattern error counter
    • Multi-lane AM status (locked and aligned/not locked and aligned)
    • FEC Corrected code word count (with FEC enabled)
    • FEC corrected 1s and 0s counts
    • FEC Uncorrected code word count (with FEC enabled)
    • FEC symbol error counter (with FEC enabled)
    • FEC degrade SER (with FEC enabled)
  • Clause 45 MDIO register set
  • Error detection and interrupt reporting