SFI-S : 100G Digital Core


The Precise-ITC Scalable Serdes Framer Interface Digital Core IP implements the digital portion of the SFI-S interface (OIF-SFI-S-01.0). The SFI-S interface is used to connect communication microchips with 80-160 Gbps or higher bit-rate.  It is a scalable interface which can support 4 – 20 lanes and each lane can have bit-rate over 6.25 – 11.2 Gbps.

It features an efficient design with a small footprint, minimizing device resource requirements and lowering component costs.

Key Features

  • Fully compliant with OIF-SFI-S-01.0
  • Supports 4 – 20+ lanes and beyond
  • Provides easy I/O connections to Serdes components
  • Optional processor interface with 32-bit registers

Transmit

  • Programmable bit inversion at system input
  • Programmable bit inversion at PHY output
  • Programmable PHY output lane swap
  • Programmable deskew (DSC) channel reference frame
  • Programmable inversion of system input data on odd phase data element
  • Supports fixed and PRBS test pattern generation.  Test pattern can be assigned to an individual lane or striped across data lanes

Receive

  • Supports lane-to-lane deskew of up to +/- 40 UI (i.e. 80 UI)
  • Programmable bit inversion at PHY  input
  • Programmable bit inversion at system output
  • Programmable PHY input lane swap
  • Programmable deskew (DSC) channel reference frame
  • Programmable inversion of system output data on odd phase data element
  • Supports fixed and PRBS test pattern monitoring.  Test pattern can be assigned to an individual lane or striped across data lanes

Block Diagram

 

Precise-ITC Scalable Framer Interface Digital Core (SFI-S)