Verification & Design – ASIC / FPGA


The Precise-ITC Engineering Team consists of highly skilled and experienced engineers with diverse and varied backgrounds.  We have worked for APM(AMCC), Cisco, PMC-Sierra, Alcatel-Lucent, JDSU, Cortina Systems, Nortel Networks, and other privately-owned Ottawa-based hi-tech companies. We have a total of over 200 years of IC design engineering experience in telecommunication devices. High speed, high capacity and complexity is our expertise.

We specialize in the following areas :

  • ASIC / FPGA Professional Consulting Services
  • Custom Intellectual Property (IP) Development
  • Custom Embedded System Development

Here are the highlights for our team

Verification Engineers

  • Average over 10+ years (UVM, OVM, VMM) each
  • coverage-driven constraint random methodology
    • SystemVerilog UVM, VMM, OVM
    • UVC development, and system-level test development
    • Specman E –  eRM & UVM
  • Projects : 400G OTN, 100G Ethernet, Network Proc
  • system verification on complex 250+ Mil gate network ASIC
  • Some with over 20 years – traditional directed test approach
  • Background
    • ALU, APM, Ciena, Cisco, Nortel, PMC-Sierra

Design Engineers

  • Average over 16+ years experience each
  • Complex data-path, DSP algorithm and pipelining designs
  • Architecture to RTL handoff / GDSII
  • Verilog/VHDL RTL coding
  • Expertise : OTN, Ethernet, Nx100G datapath design
  • Projects : 400G OTN, Network Proc, Nx100G any-rate mapper
  • ASIC
    • Logic Synthesis
    • Static Timing Analysis (primetime STA)
    • Power Analysis
    • ATPG/DFT test insertion and generation
  • FPGA
    • Vivado/ISE, Quartus, Libero IDE
  • Interface experience
    • TFI-6, SFI-S, PCIE, OTL4.x, Interlaken, CDAUI, CAUI, XLAUI, XAUI, AXI4
  • Background :
    • ALU, APM, Ciena, Cisco, Nortel, PMC-Sierra

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Physical Design Engineers

  • Average over 20+ years experience each
  • Over 18 ASICs taped-out
  • RTL handoff to GDSII or Netlist handoff to GDSII
  • CMOS & SOI (from 350nm to 28nm) , 250+ Mil gates
  • Summary :
    • DFT flow from RTL/gate to GDSII
    • ATPG, MBIST, JTAG+boundary SCAN
    • Synthesis, Physical Synthesis
    • Layout, Place and Route
    • STA/PX (timing & power) closure
    • Formal Verification
    • Power optimization
    • Timing closure and ECO flow
    • Advanced DFT architecting for complex SOC
  • Tools : Cadence, Synopsys and Mentor flows
  • Background : Nortel Semi, STM

Project Highlights

– specialized in Telecom ASICs / FPGAs / IPs
– past projects : 10G/40G/100G/400G OTN and 1G/10G/40G/100G Ethernet, SONET/SDH, GPON, EPON, ATM and IP switching and processors
– Interfaces : PCI express (PCIe), AXI, AHB, XAUI, OTL, PCI, 60x, SFI-S, SFI5, SFI4, TFI-X,  I2C, SPI, MDIO