200GE / 400GE PCS IP Core


200/400G Ethernet PCS Cores [802.3bs-D3.0]

The Precise-ITC 200G/400G Ethernet IP cores are cutting edge solution to the 200G/400G Ethernet application.  It supports the Physical Coding Sublayer (PCS) for 64B/66B, type 200G/400GBASE-R function based on the IEEE 802.3bs (DRAFT-3.0 TBD).

There are 3 PCS Cores : 200GBASE-R only, 400GBASE-R only and 200G/400GBASE-R combined Core. The PCS layer core supports 64B/66B encoding for transmission of data and control characters, 256/257B transcoding, FEC calculation, and data distribution to support multiple lanes in the Physical Layer.   It includes insertion and extraction points for connection to an OTN layer.  This core is suitable for use in switch or interface cards or any application that requires a PCS for 200G/400GbE. For a complete Ethernet solution, the PCS Core seamlessly integrates with the Precise-ITC 200G/400G MAC cores.

200G/400G PCS Core Features

PCS TX Core

  • 64B/66B encoding of incoming MII signal
  • Idle block removal (to reduce overhead for AM insertion)
  • 256/257B transcoding (to reduce overhead for FEC insertion)
  • Scrambling (optional bypass)
  • Alignment Marker (AM) insertion. Unique marker portion of AM for each lane is s/w configurable.
  • KP4 (RS544,514) Forward Error Correction (FEC) parity calculation and insertion (2x interleaved)
  • 200G : Symbol Distribution so that output is composed of 8 lane of 80-bits (version F) or 40-bits (version A) each
  • 400G : Symbol Distribution so that output is composed of 16 lane of 80-bits (version F) or 40-bits (version A) each
  • Test pattern generation (scrambled idles)
  • Clause 45 MDIO register set
  • Error detection and interrupt reporting

 PCS RX Core

  • 200G : Alignment lock and lane deskew of 8 lanes. Unique marker portion of AM for each lane is s/w configurable
  • 400G : Alignment lock and lane deskew of 16 lanes. Unique marker portion of AM for each lane is s/w configurable
  • Lane reordering
  • KP4 (RS544,514) FEC decoding and error correction (2x interleaved)
  • Alignment marker removal
  • Descrambling (optional bypass)
  • Reverse 256/257B transcoding
  • 64B/66B decoding to MII signal
  • Test pattern monitoring
  • Clause 45 MDIO register set
  • Error detection and interrupt reporting
  • Loopback from TX MII to RX MII
  • Performance Monitoring and Statistics
    • Dynamic skew measurement for each lane
    • FEC Corrected code word count
    • FEC Uncorrected code word count
    • FEC symbol error counter
    • PCS Status – link up/down
    • High bit error rate (hi-BER)
    • Degraded SER
    • Hi-SER
    • BER counter
    • Test pattern error counter
    • Multi-lane AM status (locked and aligned/not locked and aligned)
    • Lane mapping for each of physical lanes 0-7 / 0-15