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USB 3.0 Core - Super Speed USB at 5 Gbps Print E-mail

USB 3.0 function Core

  • USB 3.0 PHY-Core layer function
  • USB 3.0 PIPE interface* with the choice of 8, 16 & 32 bit buswidth
  • Support SuperSpeed Mode (5 Gbps),
  • Support Full Speed Mode (12 Mbps) and Low Speed Mode (1.5 Mbps)
  • Optional Hi-Speed Mode (480 Mbps) support

Note :

* This interface signals are like those in PCI Express PIPE interface.

 
SP80 - 8-bit MCU Print E-mail

SP80 - 8-bit MCU

  • 8-bit microcontroller unit
  • 16-bit address bus and 8-bit data bus
  • binary compatible to Z80 and 8080 CPUs
  • cycle timing compatible with Zilog Z80
  • perfect core for FPGA or ASIC
  • timer, PIO, MMU and other IPs can be easily integrated with this macro
  • deliverables - RTL (verilog/VHDL) source and testbenches
 
Floating Point Unit (FPU) Print E-mail

Floating Point Unit (FPU) - IEEE 754-2008 compliant

  • IEEE 754-2008 standard compliant floating point unit
  • support single or double precision
  • support addition, subtraction, multiply, division and square-root operations
  • support 4 rounding modes
  • generic address/data/mode access buses allow easy integration with any MCU or CPU
  • deliverables - RTL (verilog/VHDL) source codes and testbenches
New! Available since Dec 2009.
 
Design-For-Test (DFT) IPs Print E-mail

Boundary Scan IP and Insertion Tools

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  • IEEE standard 1149.1 Compliant
  • BSCAN cell, TAP & Instructions
  • Customized Insertion Services Available

Memory BIST for SRAM and ROM 

  • Algorithms - March Variants, Checkerboard,  walking 1/0, ROMBIST
  • Custom algorithm development
  • Optional - Custom walking signature support
  • Optional - Redundant Row/Column SRAM support
  • Optional - Debug capability
  • Customized integration services available
 
10 G Ethernet 802.3ae IPs Print E-mail

10G Ethernet MAC Core

  • IEEE 802.3 MAC compliant
  • XGMII phy-side interface or XAUI interface*
  • FIFO-like system-side interface
  • MDIO Master and PHY control
  • Deliverables - Synthesizable RTL and behavioural test suite

10G Ethernet SecurMAC© Core

  • transparent security layer function
  • IEEE 802.3 MAC compliant
  • XGMII phy-side interface or XAUI interface*
  • FIFO-like system-side interface
  • MDIO Master and PHY control
  • Deliverables - Synthesizable RTL and behavioural test suite

System Solutions

10G-BASE-X Ethernet SecurMAC© 

  • integrated 10G Ethernet SecurMAC©
  • Phy side XAUI interface
  • PCI Express System-side Interface (for complete 10G Ethernet adapter)
  • available in Altera/Xilinux FPGA or ASIC SOC or OEM ASIC
 
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