Scalable Serdes Framer Interface (SFI-S)

• SFI-S digital core - TX/RX
• Parameterizable lanes, bus width
• Digital core fully compliant to OIF-SFI-S-01.0 Specification
• Perfect for ASIC or FPGA realization
• Easy to interface with any parallel to serial serdes
• Both UVC (verification IP) and/or RTL codes are available

10G Ethernet MAC Core

• IEEE 802.3 MAC compliant
• XGMII phy-side interface or XAUI interface*
• FIFO-like system-side interface
• MDIO Master and PHY control
• Deliverables - Synthesizable RTL and behavioural test suite

10G Ethernet SecurMAC© Core

• transparent security layer function
• IEEE 802.3 MAC compliant
• XGMII phy-side interface or XAUI interface*
• FIFO-like system-side interface
• MDIO Master and PHY control
• Deliverables - Synthesizable RTL and behavioural test suite

System Solutions

10G-BASE-X Ethernet SecurMAC© 

• integrated 10G Ethernet SecurMAC©
• Phy side XAUI interface
• PCI Express System-side Interface (for complete 10G Ethernet adapter)
• available in Altera/Xilinux FPGA or ASIC SOC or OEM ASIC

We can help in all area of ASIC/FGPA flow from idea and concept to final GDSII tapeout. Here briefly outlines what we can provide. And, we can do a lot more.

• Architecting and concept
• ASIC flow/environment setup
• ASIC/FPGA design and verification services (front-end)
• Custom IP development
• Design re-optimization
• SOC integegration
• ASIC Synthesis, DFT, STA, Formal Verification, ATPG
• ASIC Physical Design (Layout - back-end)
• FPGA Synthesis and optimization
• Production Test Generation and Consulting